1. Field of the Invention
This invention relates to a method of driving a solid-state imaging device and more particularly, to a method of driving a solid-state imaging device in a full frame reading type.
2. Description of the Prior Art
Recently, charge coupling device (CCD) image sensors offer a wide variety of applications as the imaging device of an electronic still camera in addition to the video camera to be used for home-use, industrial and broadcasting applications purpose.
Inter-line transfer CCD image sensor which is an imaging device developed for the video camera use is generally designed so that interlace motion can be effected by means of either frame storage reading method or field storage reading method. In case of the electronic still camera, however, the vertical resolution will be reduced to half with one field video signal of the interlace motion. As a result, it is structured such that one transfer step is assigned to one pixel in order that signal charges of all pixels can be simultaneously read out to be transferred independently.
FIG. 1 shows a conventional solid-state imaging device using an inter-line transfer CCD image sensor for full frame reading. In FIG. 1, when receiving an optical video signal, a photo diode 1 provided in each pixel photoelectrically converts the optical video signal into a signal charge to store. These signal charges thus stored in the photodiodes 1 all are read out simultaneously through transfer gates 3 provided in every pixel and transferred to vertical CCD registers 2 of three-phase drive in parallel and independently (inter-line transfer system). The vertical CCD registers 2 each transfers the signal charges thus received to a horizontal CCD register 4 in one horizontal blanking period of time by in an one-by-one transfer step. The horizontal CCD register 4, to which one end of each of the vertical CCD registers 2 is connected, transfers the received signal charges to an output circuit 5 provided on one end of the register 4. The output circuit 5 converts each of the signal charges thus transferred into a voltage signal in accordance with its charge quantity. In addition, the reference numeral 6 indicates an overflow drain for absorbing excess charges and unnecessary charges. In this solid-state imaging element, the overflow drain 6 can be formed in a longitudinal type structure for absorbing excess charges within the photodiode range into a substrate disposed just under such photodiode range.
FIG. 2 shows in details a structure of the vertical CCD register 2 of the solid-state imaging device shown in FIG. 1. The vertical CCD register 2 has a plurality of transfer steps each having three vertical transfer electrodes V1, V2 and V3, and a horizontal transfer electrode H2 on its one end. In this case, each transfer step is assigned by a pixel. In addition, a signal charge generated through the photodiode 1 provided by a pixel is first transferred to the vertical transfer electrode V2 of the corresponding step. In FIG. 2, three transfer steps are shown corresponding to the three photodiodes PD1, PD2 and PD3 for the simplification of explanations.
FIG. 3 is a timing chart for explaining a conventional method of driving the solid-state imaging device shown in FIGS. 1 and 2. First, the signal charges stored in the photodiodes 1 all are simultaneously read out to each of the vertical CCD registers 2 in response to a reading pulse (TG pulse) supplied to each of the vertical transfer electrodes of each vertical CCD register 2 in the vertical blanking period of time VBLK. The signal charges thus read out are transferred by parallel in an one-by-one line step to the horizontal CCD register 4 in response to a line shift pulse A in one horizontal blanking period of time HBLK. The horizontal CCD register 4 having received one line part of the signal charges from the vertical CCD registers 2 transfers them to the output circuit 5 in a successive manner.
FIG. 4 is a detailed timing chart for explaining the transfer state of signal charges of the vertical CCD register 2 in response to the line shift pulse A shown in FIG. 3, and FIG. 5 shows a transfer state of a signal charge at the times of a to g shown in FIG. 4. The line shift pulse A shown in FIG. 3 consists practically of three pulses as shown in FIG. 4, which are supplied successively to the vertical transfer electrodes V1, V2 and V3 at such a timing that is slightly shifted.
Referring to a signal charge QN read out from a photodiode PDN in response to the TG pulse, at a time of a, a voltage pulse is applied to each electrode V2 thereby to form a potential well under the electrode 2, so that the signal charge QN is stored into the potential well thus formed under the electrode V2 directly connected to the photodiode PDN as shown in FIG. 5. Next, at a time of b, a potential well is formed under the electrode V3 by a voltage pulse applied to each electrode V3, so that the signal charge QN is stored into a potential well formed under both the electrode V2 and the electrode V3 of the photodiode PDN. Then, at a time of c, the supply of a voltage to each electrode V2 is stopped, so that the potential well formed thereunder is disappeared. As a result, the signal charge QN is transferred to the potential well formed under the electrode V3 between the photodiode PDN and the horizontal transfer electrode H2.
Further, at a time of d, in response to a voltage pulse applied to each of the electrodes V1, a potential well is formed thereunder, so that the signal charge QN stored in the potential well formed under the electrode V3 between the photodiode PDN and the horizontal transfer electrode H2 is stored further in a potential well formed under the electrode V1, which means that the signal charge QN is stored in a potential well formed under both the electrode V3 and the electrode V1 adjacently disposed on the right side thereof as shown in FIG. 5. Then, at a time of e, the supply of voltage to the electrode V3 is stopped, so that the signal charge QN stored under both the electrodes V1 and V3 is moved to the potential well under the electrode V1. Subsequently, at a time of f, the voltage supply to each electrode V2 is re-started, and a potential well is formed under the electrode V2 adjacently disposed to said electrode V1 between the photodiode PDN and the horizontal transfer electrode H2, so that the signal charge QN thus stored in the potential well under said electrode V1 is further stored in the potential well formed under the electrodes V1 and V2. Also, at a time of g, the voltage supply to each electrode V1 is stopped, so that the signal charge QN stored under said electrodes V1 and V2 is moved to the potential well formed under the electrode V2. Thus, one transfer step of transferring the signal charge QN is completed.
The signal charge QN moved to the electrode V2 adjacent to the horizontal transfer electrode H2 is transferred successively to a potential well formed under the horizontal transfer electrode H2 and sent to the output circuit 5 through the horizontal CCD register 4. In addition, referring to a signal charge QN+1 read out from another photodiode PDN+1, it is transferred in the same manner that is explained above.
In the conventional method of driving a solid-state imaging device described above, signal charges are transferred through the vertical CCD registers 2 by in an one-by-one transfer step in one transfer period of time HBLK, so that the signal charges of two photodiodes 1 adjacently disposed to each other in the vertical direction cannot be added, thus making impossible to effect field storage. As a result, with such a driving method as shown above, the solid-state imaging device cannot be used for the video camera applications purpose, resulting in such a disadvantage that it is limited to be used for the still-picture camera applications purpose.
Accordingly, an object of this invention is to provide a method of being driving a solid-state imaging device capable of used not only for the still camera application purpose but also for the video camera application purpose.